Dynamic Random Access Memories (DRAMs) include an array of memory cells contained on a semiconductor integrated circuit chip (ICs). The memory cells are arranged in rows and columns (e.g., 1-Mbit, 4-Mbit, 16-Mbit, 64-Mbit). Each cell stores a bit of information by the presence or absence of an electric charge on a capacitor. In a DRAM, refresh circuitry is provided for "refreshing" the stored charge (i.e., restoring to full charge a capacitor that is partially discharged).
With the latter generations of DRAMs, various device options have been offered by semiconductor manufacturers to the customers who use the DRAMs in their electronic equipment. These device options provide different functional characteristics in a memory device and can be used to improve the performance of a DRAM or its suitability for a particular application.
A large percentage (e.g., over 90%) of DRAMs are sold with a fast page mode function and are termed fast page mode DRAMs. A fast page mode operation in a DRAM allows faster data operations within a row address defined page boundary. In general, this is accomplished by holding the row address (RAS) signals low and strobing in different column addresses (CAS) signals to execute faster memory cycles.
Another performance option in a DRAM is known as extended data out, or sometimes referred to as hyper page mode. A DRAM that includes this feature is termed an EDO DRAM. With an EDO DRAM, blocks of data can be outputted from the DRAM similar in fashion to the Fast-Page Mode DRAM but at a faster cycle rate. This is accomplished because the CAS signal, transitioning high, no longer controls the output buffer thereby providing for pipelined data flow. This allows data to be read and processed faster. In general, an extended output is accomplished by configuring a DRAM, such as a fast page mode DRAM, so that the CAS signal no longer tristates the I/O buffer when CAS goes into precharge.
Two other types of DRAM are known as a write per bit (WPB) DRAM and a static column DRAM. A write per bit (WPB) DRAM is configured with a RAS/WE key and mask register to provide latching mask data if WE is low when RAS transitions from a high to a low which the mask is now able to define which data inputs will be allowed to be passed through on the subsequent CAS transitions (low). A static column DRAM is configured similar to a Fast-Page-Mode DRAM with the exception that the column address buffer does not latch the data at CAS time (CAS going low) thereby eliminating the need for tCAC (i.e., access time from CAS). This provides faster page cycles since the CAS signal is no longer required to release data from the DRAM. A WPB DRAM and a static column DRAM can also be configured to have an extended data output.
These various device options in a DRAM typically utilize the same memory array but require different interface circuitry for addressing, enabling output and refreshing the memory cells within the memory array. The interface circuitry includes logic gates and CMOS transfer devices formed on board the chip to produce a desired circuit arrangement. The desired option is typically implemented during wafer fabrication utilizing appropriate mask sets to construct the required circuitry.
One disadvantage of this approach is inflexibility. The configuration of the chip is set at the time of manufacture and cannot be changed. A manufacturer must therefore fabricate large numbers of different wafers to produce the different types of chips needed to satisfy different markets. This increases product development costs and the time to market for a product. Similarly, customers who use ICs may be required to inventory several different types of chips for use in their products.
Another approach is to include all of the device options in one basic mask set and then derive the desired final configuration of the chip in the assembly operations. As an example, with bond programming, the chip configuration may be selected by either bonding to a pad or leaving the pad open. For achieving the desired circuit configuration, a bonded pad may connect to certain circuitry and an unbonded pad may be taken to a default potential. U.S. Pat. No. 5,303,180 to McAdams describes such a bond programming arrangement. Programmable links such as fuses and laser actuated links are also sometimes used to effect a device option.
These approaches are also somewhat inflexible and cannot always be easily implemented by a customer. What is needed is a method for selecting different performance options in a DRAM that does not require expensive manufacturing or assembly operations.
Accordingly, it is an object of the present invention to provide a DRAM configured with different performance options that can be enabled using appropriate logic signals. It is another object of the present invention to provide a DRAM such as a fast page mode DRAM, a WPB DRAM or a static column DRAM that can be configured as an EDO DRAM upon the input of appropriate logic signals.